Principal Signal Processing Engineer

Brendan Garvey received his B.S. in Electrical Engineering from Arizona State University. Brendan has over 25 years of experience in the model development, simulation, design, and FPGA implementation of digital communications, wireless, and DSP sub-systems. Software tools and languages: Brendan has experience with MATLAB, VHDL, Verilog and SystemVerilog, digital logic simulators, the Catapult C high-level synthesis tool, and C++.

From 1988 through 1998, Brendan worked at SiCOM in Scottsdale, Arizona on various signal processing and digital communications blocks. He was the sole developer of a Hilbert Transform ASIC which he took from design to release to the foundry. He also performed simulations and trade-off studies on a charge-pump based symbol tracking loop for a Digital Video Broadcast (DVB) demodulator ASIC.

From 1998 through 2003, Brendan worked for Motorola in Chandler, Arizona. Here his tasks included FPGA design, research and simulation of an all-digital symbol tracking loop based on a farrow interpolation structure, also analysis and simulation of a carrier tracking loop of an existing 64/256-QAM design.

From 2003 through 2005, Brendan worked for Spectrum Astro in Gilbert, Arizona. Here he was the Responsible Design Engineer for a satellite uplink/downlink board. Responsibilities included FPGA design modifications and board-level testing.

From 2005 through 2015, Brendan worked at General Dynamics Mission Systems in Scottsdale, Arizona. Here Brendan worked on multiple modem and waveform designs, helping to take designs from specifications and system models into FPGA implementation. He developed hardware micro-architectures for PSK spread and non-spread demodulators. He performed high-level design, detailed design and characterization of an OQPSK demodulator. He also worked on a radar program where he designed the digital downconvert module.

In 2015, Brendan started his own LLC, where he conceived, designed and implemented a cloud-based simulation framework intended to accelerate the simulation of C-based wireless communications and radar systems. The purpose of this simulation framework is to give the user the ability to create their own virtual cluster within the Amazon Elastic Compute Cloud (EC2), while hiding the complexity and implementation details. The tool was taken to the proof-of-concept stage: an all-digital symbol tracking loop was simulated on a 69-node cluster, with a speedup of 56. Brendan actively worked on this project through 2017.

From 2018 through 2021, Brendan worked as a contractor doing C++ software development. He was part of a modeling team responsible for creating a cycle-accurate C++ model of a custom scalable processor. Brendan was specifically responsible for creating a C++ model of an HBM (high-bandwidth memory) controller.